1. Field of the Invention
The present invention relates generally to interconnect structures, and more particularly to methods for reducing interconnect structure signal delays.
2. Description of Related Art
At current levels of chip integration, interconnect signal delay has become a substantial factor in chip speed. If an interconnect structure has a signal wire running parallel to other signal wires for a relatively long distance, the effective capacitance of the signal wire that is seen by the driver of that wire depends on the signal switching activities on the neighboring signal wires.
If a signal wire is situated between two other signal wires and signals on the two other signal wires switch in one direction nearly simultaneously with a signal switch on the middle signal wire in the opposite direction, the effective capacitance seen by the driver of the middle signal wire is doubled. Conversely, if the signals on the two other signal wires switch simultaneously with a signal switch on the middle signal wire in the same direction, the effective capacitance seen by the driver of the middle signal wire is zero.
This phenomenon is referred to in the literature as the Miller effect. In current submicron technologies where most of the capacitance of a wire is to adjacent neighboring wires, the Miller effect results in a worst-case signal delay on the wire, to a first order, which is twice the signal delay when signals on the neighboring wires are quiet.
FIG. 1 is an illustration of a common method used in submicron technologies to negate the Miller effect in interconnects. Wire 110 is a signal wire that is part of a long interconnect and so includes three buffers 111_1 to 111_3. The segment of wire 110 between each of buffers 111_1 to 111_3 is shielded.
Specifically, segment 110A of wire 110 between buffers 111_1 and 111_2 is shielded by wires 112_1 and 112_2. Segment 110B of wire 110 between buffers 111_2 and 111_3 is shielded by wires 113_1 and 113_2.
The capacitance between segment 110A and wire 112_1 is represented by capacitors 114_1 to 114_3. The capacitance between segment 110A and wire 112_2 is represented by capacitors 115_1 to 115_3.
The capacitance between segment 110B and wire 113_1 is represented by capacitors 116_1 to 116_3. The capacitance between segment 110B and wire 113_2 is represented by capacitors 117_1 to 117_3.
To prevent the increase in the effective capacitance due to the Miller effect, each end of a shield wire is tied to the power supply ground as illustrated in FIG. 1. Hence, the shields provided by wires 112_1, 112_2 and 113_1, 113_2 are guaranteed not to switch signal state. Consequently, the effective capacitances seen by the driver of the signal wire was constant, independent to a first order of signal switching activities on neighboring wires.
Various techniques have been used to provide grounded shield for signal wires in an interconnect structure. See for example, U.S. Pat. No. 6,081,022 entitled xe2x80x9cClock Distribution Network with Efficient Shielding,xe2x80x9d of Sundari S. Mitra et al. issued on Jun. 27, 2000.
In one embodiment of the present invention, an interconnect structure includes a signal wire and an active shield line adjacent to, but removed from, the signal wire. A signal, which is substantially simultaneous to a pulse on the signal wire, is asserted on the active shield line.
The interconnect structure also includes another active shield line adjacent to, but removed from, the signal wire. A signal driver is connected to the signal wire. The signal driver drives the pulse on the signal wire. A shield driver is connected to the active shield line. The shield driver asserts the signal on the active shield line substantially simultaneous with the pulse. Another shield driver is connected to the another active shield line. The another shield driver asserts a signal on the another active shield line substantially simultaneous with the pulse.
The effect of the simultaneous signals on the signal wire and the active shield lines is to effectively cancel any lateral capacitances between these lines. This reduces the total capacitance seen by the signal driver and therefore significantly reduces the signal delay of the signal wire.
Hence, in one embodiment of this invention, a method for reducing lateral capacitance in an interconnect structure includes:
driving a pulse on a signal wire; and
asserting a signal substantially simultaneous with the pulse on an active shield line of the interconnect structure where the active shield line is adjacent to, but removed from, the signal wire.
The active shields can be used in a wide variety of applications where the Miller effect is a problem. For example, the active shields can be used at the board level, the integrated circuit level, or the on-chip level. The active shields are particularly advantageous for a submicron on-chip interconnect structure where the lateral capacitance makes up a substantial component of the total capacitance associated with a signal line in the interconnect structure.